What does synthesizable mean in vhdl

You should upgrade or use an alternative browser. Thread starter hemant Start date Dec 15, Status Not open for further replies. Non-synthesizable can also mean the compiler could convert the HDL into hardware, but for some reason it doesn't do it, usually because it requires too much effort, or the target hardware doesn't adequately support it. Common examples are floating-point arithmetic and precise time delays. The statement which directly can be used to generate the Hardware called as Synthesizable statments.

The statements which can't make any hardware is known as Non-synthesizable. Ex: wait, after statements. They can not generate any hardware. See for generating delay we have counter. So 'wait' as such will not do anything. As far simulation is concern it will show you same output but after synthesis it will not. Please correct if I am wrong anywhere. Similar threads J. Synthesizable VHDL code Only use constructs that can be synthesized when writing code that will run on an FPGA!

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